As electronic devices and systems continue to evolve, their operating speeds continue to increase. However, some components of such devices and systems may operate at a lower speed, and therefore may not be compatible with, or may limit, high speed devices systems. Because of the high data rates of many networking applications, it may be necessary to multiplex the input data words operating at a high frequency into a larger data word, comprised of several smaller data words, operating at a lower frequency. One conventional networking standard enables the development of interoperable products and services for data switching and routing using optical networking technologies, provides one such standard in which this must be done. In this networking standard, for example, the interface data bus is 16-bits wide and operates dual-data-rate (DDR) at up to 500 MHz. In order to internally process that data in a device operating at a lower speed, it is necessary to multiplex that data into an internal format of a wider parallel bus operating at a lower clock frequency (i.e. 64-bits at 250 MHz). Conversely, when writing data out, it is necessary convert the data from the internal parallel bus at the lower frequency to the external 16-bit dual-data-rate format at the higher frequency. In this application, between one and nine 16-bit data words may be written into the memory per clock cycle. Because of the multiplexing necessary to send one 16-bit DDR word at 500 MHz, the internal logic must read four 16-bit words from memory per 250 MHz clock cycle.
The ability to write a variable number of words, such as a Byte-Addressable memory in which a portion of the memory can be written to, is known. A barrel shifter has the ability to shift or align output data with respect to the input data alignment. Similarly, a memory has the ability to store data so that there are no gaps between data words. However, these logical functions, either independently or when used together, are not sufficient to solve the problem of inefficient data transfer caused by idle words in a data path. While the barrel shifter provides the ability to align and shift the input data, it allows for no shift-independent storage capability. In addition, a barrel shifter provides an inefficient layout because it provides that ability to shift data from any location to any other location. That is, because data can be shifted from a barrel location to any other barrel location, circuitry must be provided for each barrel slot to receive data from any other barrel slot. In a logic circuit, such as a field programmable gate array (FPGA) or complex programmable logic device (CPLD), such a requirement would require additional logic gates. Similarly, a block memory provides the ability to write a constant amount of data in, and read a constant amount of data out each clock cycle. While the block memory allows the ability to have asymmetric data widths on the read and write interfaces, the read and write operations always require the same data width. Further, there is no alignment or empty word packing capability within the block memory.
Accordingly, there is a need for an improved integrated circuit and method of outputting data from a FIFO which can operate at a lower clock rate and read or write data at a higher clock rate.